VHDL code for 4:1 Multiplexer(MUX) D.C.S-exprmnt-2

VHDL Program For 4:1 Multiplexer 

library ieee;

use ieee.std_logic_1164.all;

entity mux is

port(a,b,c,d,s1,s0:in bit;o:out bit);

end mux;

architecture behaviour of mux is

begin

process(s1,s0)

begin

if(s1='0' and s0='0')then

o<=a;

elsif(s1='0' and s0='1')then

o<=b;

elsif(s1='1' and s0='0')then

o<=c;

else

o<=d;

end if;

end process;

end behaviour;