VHDL CODE for 2:4 ENCODER

2:4 ENCODER

library ieee;

use ieee.std_logic_1164.all;

entity encoder is

port(a: in bit_vector (0 to 3); o: out bit_vector(0 to 1));

end encoder;

architecture behave of encoder is

begin

process(a)

begin

if(a="1000")then

o<="00";

elsif(a="0100")then

o<="01";

elsif(a="0010")then

o<="10";

elsif(a="0001")then

o<="11";

end if;

end process;