VHDL Code for 4:1 multiplexer using case statement DCS-II

EXPERIMENT-4

VHDL code for 4:1 MUX

library ieee;

use ieee.std_logic_1164.all;

entity mux is

port(a,b,c,d:in bit; s:in bit_vector(0 to 1);y:out bit);

end mux;

architecture behave of mux is

begin

process(s)

begin

case s is

when "00" =>y<=a;

when "01" =>y<=b;

when "10" =>y<=c;

when "11" =>y<=d;

end case;

end process;

end behave;