VHDL code for 1:4 Demultiplexer (DEMUX)

VHDL Program for 1:4 DEMUX

library ieee;

use ieee.std_logic_1164.all;

entity demux is

port(a,s1,s0:in bit; b,c,d,e:out bit);

end demux;

architecture behave of demux is

begin

process(s1,s0)

begin

if(s1='0' and s0='0')then

b<=a;

c<='0';

d<='0';

e<='0';

elsif(s1='0' and s0='1')then

b<='0';

c<=a;

d<='0';

e<='0';

elsif(s1='1' and s0='0')then

b<='0';

c<='0';

d<=a;

e<='0';

else

b<='0';

c<='0';

d<='0';

e<=a;

end if;

end process;

end behave;