VHDL CODE FOR 1:4 DEMULTIPLEXER USING CASE STATEMENT DCS-II

EXPERIMENT-4(b)

vhdl code for 1:4 demux using case statement..

library ieee;

use ieee.std_logic_1164.all;

entity demux is

port(a:in bit; s:in bit_vector(0 to 1);b,c,d,e:out bit);

end demux;

architecture behave of demux is

begin

process(s)

begin

case s is

when "00" =>b<=a;

when "01" =>c<=a;

when "10" =>d<=a;

when "11" =>e<=a;

end case;

end process;

end behave;