Vhdl code for 16:1 MULTIPLEXER using structural modelling

16:1 MUX using 4:1 mux(structural modelling)

library ieee;

use ieee.std_logic_1164.all;

entity 16:1mux is

port(I:in bit_vector(0 to 15); S:in bit_vector(0 to 3); Y:out bit);

end 16:1mux;

architecture struct of 16:1mux is

signal Z0,Z1,Z2,Z3:bit;

component Multiplexr is

port(I0,I1,I2,I3,S0,S1:in bit;y:out bit);

end Multiplexr;

begin 

m1: multiplexr port map(I(0),I(1),I(2),I(3),S(0),S(1),Z0);

m2: multiplexr port map(I(4),I(5),I(6),I(7),S(0),S(1),Z1);

m3: multiplexr port map(I(8),I(9),I(10),I(11),S(0),S(1),Z2);

m4: multiplexr port map(I(12),I(13),I(14),I(15),S(0),S(1),Z3);

m5: multiplexr port map(Z0,Z1,Z2,Z3,S(2),S(3),Y);

end struct;