VHDL code For 4-Bit Parity Checker

4-Bit Parity Checker

library ieee;

use ieee.std_logic_1164.all;

entity pairity is

port(a:in bit_vector(0 to 3);o: out bit);

end pairity;

architecture dataflow of pairity is

begin

o<=(((a(3) xor a(2)) xor a(1)) xor a(0));

end dataflow;