Vhdl code for 2:4 Decoder

2:4 Decoder using structural modelling!

library ieee;

use ieee.std_logic_1164.all;

entity decoder is

port(a,b:in bit;d1,d2,d3,d4:out bit);

end decoder;

architecture decode of decoder is 

signal abar,bbar : bit;

begin

abar<=not a;

bbar<=not b;

d1<=abar and bbar;

d2<=abar and b;

d3<=a and bbar;

d4<=a and b;

end decode;