ADAPTIVE DELTA MODULATOR CSC-II Exp-4

ADAPTIVE DELTA MODULATOR

Communication system and circuits-II

Experiment-4

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Delta modulator CSC-II Exp-3

Delta modulator

Experiment-4

Communication system and circuits-II

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VHDL code For 4-Bit Parity Checker

4-Bit Parity Checker

library ieee;

use ieee.std_logic_1164.all;

entity pairity is

port(a:in bit_vector(0 to 3);o: out bit);

end pairity;

VHDL CODE for 2:4 ENCODER

2:4 ENCODER

library ieee;

use ieee.std_logic_1164.all;

entity encoder is

port(a: in bit_vector (0 to 3); o: out bit_vector(0 to 1));

end encoder;

architecture behave of encoder is

begin

process(a)

begin

if(a="1000")then

o<="00";

elsif(a="0100")then

o<="01";

elsif(a="0010")then

o<="10";

elsif(a="0001")then

o<="11";

end if;

end process;

Vhdl code for 16:1 MULTIPLEXER using structural modelling

16:1 MUX using 4:1 mux(structural modelling)

library ieee;

use ieee.std_logic_1164.all;

entity 16:1mux is

port(I:in bit_vector(0 to 15); S:in bit_vector(0 to 3); Y:out bit);

end 16:1mux;

architecture struct of 16:1mux is

signal Z0,Z1,Z2,Z3:bit;

component Multiplexr is

port(I0,I1,I2,I3,S0,S1:in bit;y:out bit);

end Multiplexr;

begin 

m1: multiplexr port map(I(0),I(1),I(2),I(3),S(0),S(1),Z0);

m2: multiplexr port map(I(4),I(5),I(6),I(7),S(0),S(1),Z1);

m3: multiplexr port map(I(8),I(9),I(10),I(11),S(0),S(1),Z2);

m4: multiplexr port map(I(12),I(13),I(14),I(15),S(0),S(1),Z3);

m5: multiplexr port map(Z0,Z1,Z2,Z3,S(2),S(3),Y);

end struct;

Vhdl code for 2:4 Decoder

2:4 Decoder using structural modelling!

library ieee;

use ieee.std_logic_1164.all;

entity decoder is

port(a,b:in bit;d1,d2,d3,d4:out bit);

end decoder;

architecture decode of decoder is 

signal abar,bbar : bit;

Communication System - A. Bruce Carlson [Download]

Communication System

This is a Book to Learn Communication System. You can Either Purchase it on Google Books or I am Providing a Link to Download the PDF of this Book.

Computer Architecture tutorial

Tutorial sheets 1-3

Sheet-1

VHDL CODE FOR 1:4 DEMULTIPLEXER USING CASE STATEMENT DCS-II

EXPERIMENT-4(b)

vhdl code for 1:4 demux using case statement..

library ieee;

use ieee.std_logic_1164.all;

entity demux is

port(a:in bit; s:in bit_vector(0 to 1);b,c,d,e:out bit);

VHDL Code for 4:1 multiplexer using case statement DCS-II

EXPERIMENT-4

VHDL code for 4:1 MUX

library ieee;

use ieee.std_logic_1164.all;

Communication system and circuits-II TUTORIAL- 3&4

Csc-II tut sheets 3 and 4

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Communication system and circuits-II TUTORIAL

Csc-II tutorial sheets tut-1 and 2

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List of experiments-Database management system

D.b.m.s

DATA BASE MANAGEMENT SYSTEM (ETCS-357)

Exercise 1 (Data Creation)

a)

The table given in the book by “Ivan Bayross”.

a)

Client_master(client no. , name , address1 , address2 , city , pincode , state , bal_due)

b)

Product_master (product_no.,description , profit percent , unit_measure, qty_on_hand, reorder_lvl ,sell_price,cost_price)

c)

Salesman_master (salesman_no.,salesman_name , address1 , address2 , city , pincode, state , sal_amt ,tgt_to_get,ytd_sales,remarks )

d)

Sales_order (order_no.,order_date,client_no.,dely_addr , salesman_no.,dely_type , billed_yn , dely_date, order_status)

e)

Sales_order_details(order_no.,product_no. ,qty_ordered , qty_disp ,product_rate )

D.B.M.S practical

Oracle. My sql plus

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VHDL code for 1:4 Demultiplexer (DEMUX)

VHDL Program for 1:4 DEMUX

library ieee;

use ieee.std_logic_1164.all;

entity demux is

port(a,s1,s0:in bit; b,c,d,e:out bit);

end demux;

architecture behave of demux is

begin

process(s1,s0)

4:1 Multiplexer(MUX) D.C.S-exprmnt-2 Waveform

VHDL code for 4:1 Multiplexer(MUX) D.C.S-exprmnt-2

VHDL Program For 4:1 Multiplexer 

library ieee;

use ieee.std_logic_1164.all;

entity mux is

port(a,b,c,d,s1,s0:in bit;o:out bit);

end mux;

architecture behaviour of mux is

begin

process(s1,s0)

begin

if(s1='0' and s0='0')then

o<=a;

elsif(s1='0' and s0='1')then

o<=b;

elsif(s1='1' and s0='0')then

o<=c;

else

o<=d;

end if;

end process;

end behaviour;