VHDL code for Binary to GRAY

VHDL code for Binary to GRAY

DCS-II Experiment-5

library ieee;

use ieee.std_logic_1164.all;

entity b_to_g is 

port(b: in bit_vector(0 to 3); grey: out bit_vector( 0 to 3));

end b_to_g;

architecture dataflow of b_to_g is

begin

grey(0)<=b(0);

grey(1)<=b(0) xor b(1);

grey(2)<=b(1) xor b(2);

grey(3)<=b(2) xor b(3);

end dataflow;