VHDL code for Binary to Excess-3

VHDL code for Binary to Excess-3 using DATAFLOW

DCS-II experiment-5

library ieee;

use ieee.std_logic_1164.all;

entity bin_to_e3 is

port(b: in bit_vector(0 to 3); e: out bit_vector(0 to 3));

end bin_to_e3;

architecture dataflow of bin_to_e3 is

begin

e(0)<=b(0) or ( b(1)and(b(2) or b(3)) );

e(1)<=b(1) xor (b(2) or b(3));

e(2)<=not (b(2) xor b(3));

e(3)<= not b(3);

end dataflow;