Binary to Gray Using STRUCTURAL MODELLING

VHDL Code for Binary to Gray Using STRUCTURAL MODELLING

library ieee;

use ieee.std_logic_1164.all;

entity btog is

port(b3,b2,b1,b0: in bit; g3, g2, g1, g0: out bit);

end btog;

architecture structure of btog is

component xor_gate is

port(l,m:in bit;n: out bit);

end component;

begin

g3<=b3;

x2: xor_gate port map(b3,b2,g2);

x3: xor_gate port map(b2,b1,g1);

x4: xor_gate port map(b1,b0,g0);

end structure;