Dcs practical-II vhdl half adder behavioral

Half Adder Behavorial

library ieee;

use ieee.std_logic_1164.all;

entity ha2 is

port(a,b:in bit;s,c:out bit);

architecture bhv of ha2 is

begin

process (a,b)

begin

if a='o' and b='o'

then s<='0',c<='0';

elsif a='0' and b='1'

then s<='1', c<='0';

elsif a='1'and b='0'

then s<='1', c<='0';

else s<='1', c<='1';

end if;

end process;

end bhv;