D.C.S Lab-VHDL half subtractor

Half Subtractor in VHDL behavorial

library ieee;
use ieee.std_logic_1164.all;

entity hs is
port(a,b:in bit;dif,bor:out bit);
end hs;

architecture behaviour of hs is
begin
process(a,b)
begin
if(((a='0') and (b='0')) or((a='1') and (b='1'))) then
dif<='0';
bor<='0';
elsif(a='0') and (b='1') then
dif<='1';
bor<='1';
else
dif<='1';
bor<='0';
end if;
end process;
end behaviour;