Dcs practical exprmnt-2 full subtractor behavorial

Full Subtractor in VHDL behavorial

library ieee;
use ieee.std_logic_1164.all;

entity fs is
port(a,b,bin:in bit;dif,bor:out bit);
end fs;

architecture behave of fs is
begin
process(a,b,bin)
begin
if(((a='0') and (b='0') and (bin='0')) or ((a='1') and (b='0') and
(bin='1')) or((a='1') and (b='1') and (bin='0'))) then
dif<='0';
bor<='0';
elsif(((a='0') and (b='0') and (bin='1')) or ((a='0') and (b='1') and
(bin='0')) or((a='1') and (b='1') and (bin='1'))) then
dif<='1';
bor<='1';
elsif((a='0') and (b='1') and (bin='1')) then
dif<='0';
bor<='1';
elsif((a='1') and (b='0') and (bin='0')) then
dif<='1';
bor<='0';
end if;
end process;
end behave;